1. Field of the Invention
The present invention relates to a parallel capacitor of a semiconductor device, and more specifically, to a parallel capacitor of a semiconductor device in which two capacitors are connected in parallel to enhance capacitance of the capacitors.
2. Discussion of Related Art
As the level of integration in semiconductor devices increases, researches have been actively made into fabrication of a capacitor having high capacitance in a narrow area. As one of methods, there has been made an attempt on a method in which capacitors are formed in different layers in the same region and are then connected in parallel to increase capacitance.
FIG. 1 is a cross-sectional view showing the structure of a conventional parallel capacitor.
Referring to FIG. 1, the conventional parallel capacitor includes a first capacitor C1, which is formed between a first metal layer 102 and a second metal layer 109a formed on the first metal layer 102, and a second capacitor C2, which is formed between a third metal layer 113b and a fourth metal layer 120a formed on the third metal layer 113b. Each of the first to fourth metal layers 102, 109a, 113b and 120a is formed in a different layer.
In the above, a lower electrode 103 of the first capacitor C1 is electrically connected to the first metal layer 102, and an upper electrode 105 is electrically connected to a second metal layer 109a by means of a via plug 107a. Furthermore, a lower electrode 114 of the second capacitor C2 is electrically connected to the third metal layer 113b, and an upper electrode 116 is electrically connected to a fourth metal layer 120a by means of a via plug 118b. 
Meanwhile, the first and third metal layers 102 and 113, which are respectively connected to the lower electrodes 103 and 114 of the first and second capacitors C1 and C2 are electrically connected to second and fourth metal layers 109b and 120b by means of via plugs 107b, 111b and 118c. Furthermore, second and fourth metal layers 109a and 120a connected to the upper electrodes 105 and 116 of the first and second capacitors C1 and C2 are electrically connected to a third metal layer 113a by means of via plug 111a and 118a. 
An unexplained reference numeral 101 indicates a semiconductor substrate, 104 and 115 indicate dielectric films, and 106, 108, 110, 112, 117 and 119 indicate interlayer insulating films.
Through the above structure, the first capacitor C1 and the second capacitor C2 are formed to have a parallel structure while being formed in different layers of the same region.
In the above structure, in order to fabricate the two capacitors C1 and C2 in a parallel structure, at least four metal layers 102, 109a, 113b and 120a are required. Such a large number of the metal layers requires a large number of process steps, and also cause a high step to occur. Moreover, if the level of integration in a device becomes high and a design rule thus becomes small, there is a limit to formation of a multi-metal wiring. Furthermore, reliability of a process is degraded and the cost is also increased.